|
|
|
bgcolor="#FFFFFF" width="840" height="2080" border="0" cellpadding="0" cellspacing="0" valign="top" align="left"> |
 OBJECTIVES
Learning how to choose a computer by examining the parameters that influence its performance. Being able to evaluate the effectiveness of the architectural mechanisms to improve the capabilities of computers. Learning how to analyze and design combinational and sequential digital systems. Knowing the structure of the main logical components at the base of digital circuits. Knowledge of the architectural elements of a modern computer and of the structure of the processor, Memory Subsystem and Input/Output Subsystem. |
|
PREREQUISITES
Computer Science Fundamentals |
|
SYLLABUS
ELEMENTS OF DESIGN OF DIGITAL SYSTEMS
CMOS technology: NOT, NAND, NOR ports, transit port (CMOS circuit); propagation delays, output input characteristics, noise margins and their dependence on physical parameters; Boolean algebra.
Standard forms of Boolean functions and Karnaugh maps; Decoder, Encoder, Priority Encoder, Multiplexer, Demultiplexer, Look-Up-Table (LUT), Half-Adder, Full-Adder, ALU.
Introduction to hardware description languages (HDL): Verilog and creation of a simple processor with RISC-V architecture.
Introduction to sequential networks: SR latches and flip-flops, clocked-SR, SR-master-salve, D-latch, D-edge-triggered and their transistor-level realizations;
Mealy and Moore machines: VERILOG models and classical synthesis; Flip-Flop JK and T; Counters: Ripple, Serial Carry, Parallel Carry, Ring Counter; Parallel adder with serial carry-over and look-ahead report.
MACHINE ORGANIZATION AND ASSEMBLY
Principles of RISC-V microprocessors. Instructions formats and basic instructions.
Assembly: addressing mode. Function call.
Performance equation. Performance evaluation, SPEC benchmark set. Amdahl's law.
Two-pass assembler. Loading, connecting multiple modules.
IEEE-754 standard for floating-point.
Floating-point registers and instructions in the processor.
Exceptions and interrupts. Interrupt management routine. Precise and inaccurate interrupts.
MEMORY SUBSYSTEM
Types of memory. Difference between SRAM and DRAM. Reading and writing cycle in DRAM.
Memory Hierarchy and Locality Principle. Cache architecture: direct access cache. Parameters characterizing the functioning of the caches.
Associative Cache. Multi-level cache. Dependency of a computer's performance on the cache.
Virtual Memory: hardware mechanisms to support it. Paging with 2 or more levels and with a reverse table. TLB: Translation Lookaside Buffer.
I / O AND COMMUNICATIONS
Types of buses. Synchronous and asynchronous exchange protocol. Arbitrage (master / slave, daisy-chain). Overview of PCI buses.
Drive devices: polling, interrupt, DMA techniques.
Example of internal complexity of the chips: timer 8254, UART 16550A.
Communications on serial buses (packetization, Ethernet, USB).
PROCESSOR
Processors with pipelines. Resolving pipeline conflicts. Limits of the pipeline and outline of superscalar processors.
|
|
TEXTBOOKS
REFERENCE (ADOPTED) TEXTBOOKS
(PHRV1)
D.A. Patterson, J.L. Hennessy, "Computer Organization and Design RISC-V Edition: The Hardware Software Interface", Morgan Kaufman/Elsevier, 2017, ISBN 978-0128122754
(CORSINI)
P. Corsini, "Dalle porte AND, OR, NOT al sistema calcolatore", Edizioni ETS, 2020, ISBN 9788846759351
SUGGESTED (OPTIONAL) TEXTBOOKS
G. Bucci, "Architettura dei Calcolatori Elettronici", McGraw-Hill, 2001, ISBN 88-386-0889-X
G. Bucci, "Calcolatori Elettronici - Architettura e organizzazione", IV EDIZIONE, McGraw-Hill, 2017, ISBN 978-88-386-7546-1
G. Conte, A. Mazzeo, N. Mazzocca, P. Prinetto , "Architettura dei calcolatori", CittaStudiEdizioni. ISBN 9788825173642
P. Corsini, G. Frosini, B. Lazzerini, "Architettura dei calcolatori", McGraw Hill, 1997, ISBN 88-386-0735-4
S. Harris, D. Harris, "Sistemi digitali e architettura dei calcolatori: Sistemi digitali e architettura dei calcolatori", Zanichelli, 2017, ISBN 9788808920737.
V.P. Heuring, "Computer Systems Design and Architecture" 2ed, Pearson/Prentice Hall, 2004, ISBN 0-13-191156-2
W. Stallings, "Architettura e organizzazione dei calcolatori", Jackson Libri, 2000, ISBN 88-256-1836-0
A. S. Tanenbaum, "Structured computer organization", 4th ed., Prentice-Hall International, 1999, ISBN 0130959901
|
|
OFFICIAL SYLLABUS
|
|
|
|
|
|
